How does it work?Īs described in the user guide in this link (Xilinx PG067): Connecting the bus as-is is not feasible and that is where the AXI Chip2Chip IP comes in. If you know the AXI bus protocol (if you don’t, read this link first – press download on the left corner), you know that it sometimes contains hundreds of bits. Since the native bus for the ARM processors on the SOC devices is AXI, it makes sense to use it to connect to the other FPGAs. If you have a design with a SOC (Zynq 7000, MPSoC, or Versal) and at least one more FPGA, you might want to have a single master processor that can communicate and control the other FPGAs with high throughput. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant. The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol.
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